library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

--- Includes a bank of 32-bits registers and decode the instruction

entity registers is
	PORT (
		clk : in STD_LOGIC;

		reg1_read_addr : in STD_LOGIC_VECTOR(4 downto 0);
		reg2_read_addr : in STD_LOGIC_VECTOR(4 downto 0);

		reg_write_en : in STD_LOGIC;

		reg_write_addr : in STD_LOGIC_VECTOR(4 downto 0);
		data_inp : in STD_LOGIC_VECTOR(31 downto 0);

		data_outp1 : out STD_LOGIC_VECTOR(31 downto 0);
		data_outp2 : out STD_LOGIC_VECTOR(31 downto 0)
	);
end registers;

architecture Behavioral of registers is
	
	type registers_bank is array(0 to 31) of STD_LOGIC_VECTOR(31 downto 0);

	signal reg_bank : registers_bank  := (others => (others => '0'));
	
	attribute ram_style: string;
	attribute ram_style of reg_bank : signal is "distributed";
	
begin	
	
--	process(reg1_read_addr, reg2_read_addr, reg_write_en, reg_write_addr, data_inp)
--	begin
--	
--		if (reg_write_en = '1' and reg_write_addr = reg1_read_addr) then
--			data_outp1 <= data_inp;
--		else
--			data_outp1 <= reg_bank(to_integer(unsigned(reg1_read_addr)));
--		end if;
--		
--		if (reg_write_en = '1' and reg_write_addr = reg2_read_addr) then
--			data_outp2 <= data_inp;
--		else
--			data_outp2 <= reg_bank(to_integer(unsigned(reg2_read_addr)));
--		end if;
--	
--	end process;
	
	data_outp2 <= reg_bank(to_integer(unsigned(reg2_read_addr))) when (reg_write_addr /= reg2_read_addr or reg_write_en = '0') else data_inp;
	data_outp1 <= reg_bank(to_integer(unsigned(reg1_read_addr))) when (reg_write_addr /= reg1_read_addr or reg_write_en = '0') else data_inp;
	
	process(clk)
	begin
		if clk'event and clk = '1' then
			-- if we're supposed to write into registers
			if reg_write_en = '1' then
				-- if the dst registers is not 0
				if reg_write_addr /= "00000" then
					reg_bank(to_integer(unsigned(reg_write_addr))) <= data_inp;
				end if;
			end if;
			
		--if (reg_write_en = '1' and reg_write_addr = reg1_read_addr) then
		--	data_outp1 <= data_inp;
		--else
		--	data_outp1 <= reg_bank(to_integer(unsigned(reg1_read_addr)));
		--end if;
		
		--if (reg_write_en = '1' and reg_write_addr = reg2_read_addr) then
		--	data_outp2 <= data_inp;
		--else
		--	data_outp2 <= reg_bank(to_integer(unsigned(reg2_read_addr)));
		--end if;
			
		end if;
	end process;
	
end Behavioral;

